1. Field of the Invention
The present invention relates generally to techniques for testing circuits, and more particularly to methods and apparatus for testing with multiple scan chains using pin sharing.
2. Description of the Related Art
Scan based design is a circuit testing technique that involves converting memory/state elements into scan elements (also referred to as scan cells), and then connecting many of these scan elements into one or more serial shift registers (also referred to as scan chains) that wind through the circuit under test (CUT). Each scan chain typically begins at a scan input, traces forward through numerous scan elements, and terminates at a scan output. The scan architecture allows the circuit under test to be placed in a known data state by serially shifting test data patterns (also referred to as test vectors or scan vectors) into the scan chains through the scan inputs under the control of a scan clock. The operation of the circuit under test can then be observed by using the same scan chains to shift data out through the scan outputs.
Scan based design has become one of the most widely used design for test (DFT) techniques for testing complicated circuits such as those found on integrated circuits (ICs or “chips”). Scan based design enables the use of automatic test pattern generation (ATPG) techniques to create test vectors that provide efficient fault detection, and reduce the cost of testing ICs.
As integrated circuits become increasingly complex, however, reducing the time, and thus cost, of testing becomes more critical. With some very large scale integration (VLSI) products, e.g., system on chip (SOC), the recurring test cost can be 2, 3 and even 4 times the cost of fabricating the chip itself.
To reduce test application times, techniques involving the use of multiple scan chains have been developed. These techniques divide a single scan chain into multiple chains and allow shorter test vectors to be shifted into the circuit under test in parallel, thereby reducing the test time. Existing multiple scan chain techniques, however, require that additional valuable input/output terminals be dedicated to use as scan inputs/outputs.
Efforts to drive multiple scan chains from a single input have produced techniques that require complicated analysis of scan chain circuits and test vectors, including the recomposition of virtual circuits before ATPG can be utilized. This dramatically increases the testing overhead while only providing slight reduction in scan test time.